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1/25 MTC20136 february 2004 dedicated controller for use with adsl transceiver chips mtc20134, mtc20135 and mtc20455 ? performs adsl control functions : ? initialization procedure ? line monitoring during operation ? rate adaptive modes supports the modem control interface protocol (ctrle) embedded high speed arm microcore glueless connection to mtc20135 and mtc20455 parallel or serial modem control interface (ctrle) for glueless connection to management entities embedded uart supports code download external bus interface for 8 and 16-bit feprom and 16-bit sdram 144 pins pqfp description the MTC20136 is a dedicated controller chip, spe- cifically designed to control operations of the st- microelectronics dynamite chipset. the MTC20136 offers direct glueless interfaces to the mtc20135 and mtc20455 dmt/atm transciever and implements a complete control interface for parameters and commands exchange between transceiver and system management. all real time adsl-related functions (including eoc process- ing) are completely handled by the MTC20136. pqfp144 lfbga160 ordering numbers: part number package temp. MTC20136pq- l1 144 pin pqfp -40 /+85c MTC20136mb-i1 160 pin lbga -40 /+85c can also be ordered using kit number mtk20131 or mtc20455 adsl transceiver controller figure 1. block diagram arm microcore rom ram timer ctrle data buffer peripherals ctrle microcontroller interface logic rs232 general purpose i/os control bus 8 data 9 address external bus interface local bus MTC20136 feprom (optional) sdram mtc-20135 or mtc-20455 uart parallel i/o .com .com .com .com 4 .com u datasheet
MTC20136 2/25 functional description figure 1 is showing the global block diagram of the MTC20136. the functions can be grouped into the following: ? microcontroller ? external bus interface ? control interface (ctrle) ? peripherals ? miscellaneous microcontroller the microcontroller block includes an arm-based microcore and its associated internal memory. 16 kbytes on internal ram and 128 x 32-bit words of rom are foreseen. the rom essentially contains the boot sequence needed for code download at startup. the use of the rom by the microcore is defined by the state of the trom pin during reset. external bus interface the external bus interface extends the internal microcontroller bus for connection of external devices. in particular, the bus is used to connect to the mtc20135 or mtc20455 modem chip and to external sdram (and optional feeprom). the ctrle functional block implements the adsl modem command and data buffer and the interface logic supporting the physical interfaces of the ctrle. peripherals the peripherals block includes two uarts for rs232 interfacing to external systems and two general = purpose parallel i/o lines. miscellaneous this includes the clock circuitry, reset circuitry, test functions and configuration control signals. ctrle interfaces external bus interface the external bus interface (ebi) provides a glueless interface to 8 and 16-bit asynchronous flash ee- prom, 16 bit sdram devices and to slave devices with an i960-like 16 bit bus interface with multiplexed address and data (as available on dynamite chips). the ebi provides two chip selects (e_ncs[1:0]) to be used for memory access (sram-like), one dedicat- ed sdram chip select ((e_ncs_s) and four chip selects (e_ncs[7:4]) to be used for access to adsl slave devices. the chip selects all correspond to a fixed 1mbyte memory region in the microcontroller memory map, except for sdram access. .com .com .com .com .com 4 .com u datasheet
3/25 MTC20136 pin layout functional pin summary the signals hereunder are grouped per functional interface. figure 2. pin functional description and type per interface test interface jtag interface peripherals ebi interface ctrl-e interface misc ntrst tck tdi tms iddq t_reqa t_reqb c_clk c_a[8:0] c_notcs c_mode[1:0] c_notwr c_notrd trom eit[3:0] notcs[7:0] e_a[19:16] e_a[15:0] e_d[15:0] clk_e resetn rsrxd2 rstxd2 tdo t_ack e_clk e_ale e_nrdy e_nweo e_nwe1 c_d[7:0] c_notint c_notrdy boot_m[1:0] rsrxd1 rstxd1 pa1 pa0 .com .com .com .com .com 4 .com u datasheet
MTC20136 4/25 the table below describes the pins, organized per interface. some of these pins have a multiple function- ality. in this case both functionalities are mentioned. name i/o type description external bus interface e_a[19:16] o address bus msbs e_a[15:0] i/o address bus lsbs / testbus msbs e_d[15:0] i/o data bus / testbus lsbs e_clk o ebi clock (asic access) e_ale o address latch enable (asic access) e_ncs_0 o chip select signal (memory bank 0) e_ncs_1 o chip select signal (memory bank 1) e_ncs_s o chip select signal (sdram) e_ncs_4 o chip select signal (asic 1) e_ncs_5 o chip select signal (asic 2) e_ncs_6 o chip select signal (asic 3) e_ncs_7 o chip select signal (asic 4) e_nrdyrcv i data acknowledge e_noe o output enable e_nwe0 o write enable lsb / w/notr indication e_nwe1 o write enable msb clock bus interface clk_in i MTC20136 master clock parallel port interface pa[0] i/o port a bit[0] pa[1] i/o port a bit[1] uart1 interface rstxd1 o serial tx port rsrxd1 i serial rx port uart2 interface rstxd2 o serial tx port rsrxd2 i serial rx port interrupt interface eit_0 i external interrupt lines eit_1 i external interrupt lines eit_2 i external interrupt lines eit_3 i external interrupt lines jtag interface ntrst i-pu reset jtag interface tck i-pu jtag clock tdi i-pu test data in tms i-pu test mode select tdo o test data out reset interface resetn i reset signal (active high) boot interface trom i boot from rom select .com .com .com .com .com 4 .com u datasheet
5/25 MTC20136 boot_m0 i/o download mode .uart baudrate. (auto adjust or 9600 bps). boot_m1 i/o download mode select (ctrl-e or uart1) ctrl-e interface (parallel mode only described - see above fo r serial mode) c_a[8:0] i address bus (5 v tolerant) c_d[7:0] io data bus (5 v tolerant) c_ncs i chip select (5 v tolerant) c_nint od ctrl-e external interrupt c_mode[1:0] i ctrl-e interface bus mode (5 v tolerant) c_nwr i write indication (5v tolerant) c_nrd i read indication (5v tolerant) c_nrdy oz ready indication c_clk i serial input clock (5v tolerant) i = input, cmos levels i-pu = input with pull-up resistance, cmos levels i-pd = input with pull-down resistance, cmos levels i-ttl = input ttl levels o = push-pull output oz = push-pull output with high-impedance state od = open drain output io = input / tri-state push-pull output pqfp144 pin configuration (default value between ( )) pin# name function 1 e_a14 ebi address 2 e_a15 ebi address 3 e_a16 ebi address 4 e_a17 ebi address 5vddvdd 6 vss vss 7 e_a18 ebi address 8 e_a19 ebi address 9 eit0 external interrupt in - 0 10 eit1 external interrupt in - 1 11 vdd vdd 12 vss vss 13 eit2 external interrupt in - 2 14 eit3 external interrupt in -3 15 i_mode tracking ice mode select (0) 16 e_clk ebi clock out 17 e_ale ebi ale 18 vdd vdd name i/o type description .com .com .com .com .com 4 .com u datasheet
MTC20136 6/25 19 vss vss 20 e_nrdyrcv ebi ack in 21 e_nwe0 ebi write enable 22 e_nwe1 ebi write enable 23 e_notcs_4 ebi asic chipselect 24 vdd vdd 25 vss vss 26 boot_m0 bootmode select 27 boot_m1 bootmode select 28 pa0 general purpose io 29 pa1 general purpose io 30 trom boot mode select 31 vdd vdd 32 vss vss 33 t_reqa reserved for test (0) 34 t_reqb reserved for test (0) 35 t_ack reserved for test 36 iddq reserved for test (0) 37 resetn reset (active low) 38 tdi jtag interface 39 tdo jtag interface 40 vdd vdd 41 vss vss 42 tms jtag interface 43 ntrst jtag interface 44 tck jtag interface 45 rstxd1 uart port 1 - tx 46 rsrxd1 uart port 1 - rx 47 rstxd2 uart port 2 - tx 48 vdd vdd 49 vss vss 50 rsrxd2 uart port 2 - rx 51 testse test scan enable 52 scan_clk test scan clock 53 c_nint ctrl-e interrupt 54 vdd vdd 55 vss vss 56 clk_in master clock in 57 vss vss 58 c_nrdy ctrl-e interface 59 c_nrd ctrl-e interface 60 vdd vdd pqfp144 pin configuration (continued) (default value between ( )) pin# name function .com .com .com .com .com 4 .com u datasheet
7/25 MTC20136 61 vss vss 62 c_nwr ctrl-e interface 63 c_mode0 ctrl-e interface 64 c_mode1 ctrl-e interface 65 c_notcs ctrl-e interface 66 c_clk ctrl-e interface 67 vdd vdd 68 vss vss 69 c_d0 ctrl-e interface 70 c_d1 ctrl-e interface 71 c_d2 ctrl-e interface 72 c_d3 ctrl-e interface 73 c_d4 ctrl-e interface 74 c_d5 ctrl-e interface 75 c_d6 ctrl-e interface 76 vdd vdd 77 vss vss 78 c_d7 ctrl-e interface 79 c_a0 ctrl-e interface 80 c_a1 ctrl-e interface 81 c_a2 ctrl-e interface 82 c_a3 ctrl-e interface 83 c_a4 ctrl-e interface 84 vdd vdd 85 vss vss 86 c_a5 ctrl-e interface 87 c_a6 ctrl-e interface 88 c_a7 ctrl-e interface 89 c_a8 ctrl-e interface 90 vdd vdd 91 vss vss 92 i_bp reserved (0) 93 i_dbgrq reserved (0) 94 notcs_7 ebi - asic chip select 95 notcs_6 ebi - asic chip select 96 notcs_5 ebi - asic chip select 97 vdd vdd 98 vss vss 99 e_ncs_2 ebi - sdram chip select 100 e_ncs_1 ebi - sram chip select 101 e_ncs_0 ebi - flash chip select 102 e_noe ebi - oe pqfp144 pin configuration (continued) (default value between ( )) pin# name function .com .com .com .com .com 4 .com u datasheet
MTC20136 8/25 103 e_d15 ebi data 104 vdd vdd 105 vss vss 106 e_d14 ebi data 107 e_d13 ebi data 108 e_d12 ebi data 109 e_d11 ebi data 110 e_d10 ebi data 111 e_d9 ebi data 112 vss vss 113 vdd vdd 114 e_d8 ebi data 115 e_d7 ebi data 116 e_d6 ebi data 117 e_d5 ebi data 118 e_d4 ebi data 119 vdd vdd 120 vss vss 121 e_d3 ebi data 122 e_d2 ebi data 123 e_d1 ebi data 124 e_d0 ebi data 125 e_a0 ebi address 126 vdd vdd 127 vss vss 128 e_a1 ebi address 129 e_a2 ebi address 130 e_a3 ebi address 131 e_a4 ebi address 132 vdd vdd 133 vss vss 134 e_a5 ebi address 135 e_a6 ebi address 136 e_a7 ebi address 137 e_a8 ebi address 138 e_a9 ebi address 139 vdd vdd 140 vss vss 141 e_a10 ebi address 142 e_a11 ebi address 143 e_a12 ebi address 144 e_a13 ebi address pqfp144 pin configuration (continued) (default value between ( )) pin# name function .com .com .com .com .com 4 .com u datasheet
9/25 MTC20136 lfbga160 pin configuration pin# name function c4 e_a14 ebi address b2 e_a15 ebi address d4 e_a16 ebi address c3 e_a17 ebi address c2 vdd vdd e3 vss vss d3 e_a18 ebi address d2 e_a19 ebi address e4 eit0 external interrupt in - 0 e2 eit1 external interrupt in - 1 e1 vdd vdd f3 vss vss f4 eit2 external interrupt in - 2 f1 eit3 external interrupt in -3 f2 i_mode tracking ice mode select (0) g3 e_clk ebi clock out h1 e_ale ebi ale g4 vdd vdd g2 vss vss h3 e_nrdyrcv ebi ack in h4 e_nwe0 ebi write enable h2 e_nwe1 ebi write enable j3 e_notcs_4 ebi asic chipselect k2 vdd vdd j4 vss vss j2 boot_m0 bootmode select k3 boot_m1 bootmode select k4 pa0 general purpose io l2 pa1 general purpose io l3 trom boot mode select m2 vdd vdd m3 vss vss l4 t_reqa reserved for test (0) n2 t_reqb reserved for test (0) n3 t_ack reserved for test n1 iddq reserved for test (0) p1 resetn reset (active low) p2 tdi jtag interface m4 tdo jtag interface p3 vdd vdd n4 vss vss m5 tms jtag interface p4 ntrst jtag interface .com .com .com .com .com 4 .com u datasheet
MTC20136 10/25 n5 tck jtag interface l5 rstxd1 uart port 1 - tx p5 rsrxd1 uart port 1 - rx m6 rstxd2 uart port 2 - tx n6 vdd vdd p6 vss vss l6 rsrxd2 uart port 2 - rx n7 testse test scan enable p7 scan_clk test scan clock m7 c_nint ctrl-e interrupt l7 vdd vdd p8 vss vss n8 clk_in master clock in m8 vss vss l8 c_nrdy ctrl-e interface n9 c_nrd ctrl-e interface m9 vdd vdd p10 vss vss n10 c_nwr ctrl-e interface l9 c_mode0 ctrl-e interface p11 c_mode1 ctrl-e interface m10 c_notcs ctrl-e interface n11 c_clk ctrl-e interface p12 vdd vdd l10 vss vss n12 c_d0 ctrl-e interface p13 c_d1 ctrl-e interface m11 c_d2 ctrl-e interface n13 c_d3 ctrl-e interface n14 not connected p14 c_d4 ctrl-e interface m12 c_d5 ctrl-e interface m14 c_d6 ctrl-e interface m13 vdd vdd l11 vss vss l14 c_d7 ctrl-e interface l13 c_a0 ctrl-e interface l12 c_a1 ctrl-e interface k14 c_a2 ctrl-e interface k11 c_a3 ctrl-e interface k13 c_a4 ctrl-e interface j14 vdd vdd k12 vss vss lfbga160 pin configuration (continued) pin# name function .com .com .com .com .com 4 .com u datasheet
11/25 MTC20136 j11 c_a5 ctrl-e interface h14 c_a6 ctrl-e interface j13 c_a7 ctrl-e interface j12 c_a8 ctrl-e interface h11 vdd vdd h13 vss vss h12 i_bp reserved (0) g11 i_dbgrq reserved (0) f14 notcs_7 ebi - asic chip select g13 notcs_6 ebi - asic chip select g12 notcs_5 ebi - asic chip select e14 vdd vdd f11 vss vss f13 e_ncs_2 ebi - sdram chip select f12 e_ncs_1 ebi - sram chip select e11 e_ncs_0 ebi - flash chip select e13 e_noe ebi - oe e12 e_d15 ebi data c14 vdd vdd d11 vss vss d13 e_d14 ebi data b14 e_d13 ebi data d12 e_d12 ebi data a14 e_d11 ebi data c13 e_d10 ebi data b13 e_d9 ebi data c11 vss vss c12 vdd vdd b12 e_d8 ebi data d10 e_d7 ebi data b11 e_d6 ebi data a11 e_d5 ebi data c10 e_d4 ebi data b10 vdd vdd a10 vss vss d9 e_d3 ebi data c9 e_d2 ebi data a9 e_d1 ebi data b9 e_d0 ebi data d8 e_a0 ebi address b8 vdd vdd c8 vss vss d7 e_a1 ebi address lfbga160 pin configuration (continued) pin# name function .com .com .com .com .com 4 .com u datasheet
MTC20136 12/25 external pins these physical pins are used for different logical functions, depending on the external device which is ac- cessed. the correspondance between physical and logical functions is given in table 1 b7 e_a2 ebi address a7 e_a3 ebi address c7 e_a4 ebi address d6 vdd vdd a6 vss vss b6 e_a5 ebi address c6 e_a6 ebi address a4 e_a7 ebi address d5 e_a8 ebi address b5 e_a9 ebi address a3 vdd vdd c5 vss vss b4 e_a10 ebi address a2 e_a11 ebi address b3 e_a12 ebi address b1 e_a13 ebi address e_d[15:0] 16 bit data, multiplexed address/data e_a[19:0] 20 bit address (including commands for sdram) ncs[7:4] external chip select e_clk external clock ale address latch enable nrdyrcv ready/recover driven by selected device together with external pull-up noe output enable nwe0 write enable for lsb byte lane e_d[7:0] nwe1 write enable for msb byte lane e_d[15:8] table 1. pin name mtc20135, mtc20455 access function sdram access function sram/feprom access function e_a [19] - s_nras e_a [19] e_a [18] - s_ncas e_a [18] e_a [17] - s_dqm0 e_a [17] e_a [16] - s_dqm1 e_a [16] lfbga160 pin configuration (continued) pin# name function .com .com .com .com .com 4 .com u datasheet
13/25 MTC20136 memory map modes three modes are defined : a) normal mode: the internal ram is mapped in the lower part of memory. this is the normal operating mode, it allows maximum speed access to exception vectors. b) normal boot mode: if the trom external pin is high at reset, the MTC20136 boots from an external feprom. c) internal boot mode: if the trom external pin is low at reset, the MTC20136 boots from its internal rom. this mode can be used to perform code download from a host. boot modes are used at reset time. boot_m0 andboot_m1 on pin 26 and 27 conrol the port to be used for downloading the code into the sdram after bootup. this when trom is low. mtc20135, mtc20455 access the MTC20136 directly connects to the mtc20135 without glue logic. following features are provided for mtc20135 access : ? 16 bit multiplexed address/data bus giving 64kbyte address space per mtc20135. ? synchronous ready-controlled operation - control signals : ncs[4:7], e_clk, ale, w/nr, nrdyrcv ? little endian byte ordering on 16 bit bus - nrdyrcv timeout mechanism the timing diagram of the access to the mtc20135 or mtc20455 is shown in figure 3: pin name mtc20135, mtc20455 access function sdram access function sram/feprom access function e_a [15:0] - s_a [11:0] e_a [15:0] e_d [15:0] ad [15:0] s_q [15:0] e_d [15:0] e_ncs [1:0] - - e_ncs [1:0] e_ncs [7:4] ncs [7:4] - - e_ncs_s - s_ncs - e_clk e-clk s_clk - e_ale ale - - e_nrdyrcv nrdyrcv - - e_noe - - e_noe e_nwe0 w/nr - e_nwe0 e_nwe1 - s_nwe e_nwe1 boot_m1 (pin27) boot_m0 (pin26) 0 1 9600 bps via serail port 1 1 0 par. ctrl-e 1 1 par.ctrl-e table 1. (continued) .com .com .com .com .com 4 .com u datasheet
MTC20136 14/25 figure 3. access to mtc20135, mtc20455 sdram the sdram interface allows a glue-less interconnection of 1 sdram. following features are provided for sdram access. ? 16 bit databus and 12 bit address bus. ? control signals : s_ncs, s_nras, s_ncas, s_nwe, s_dqm[1:0 control signal timing all sdram actions are triggered at the rising edge of its clock. timing diagrams for a burst of four 16-bit accesses to 16-bit sdram (figure 3 and figure 4) show the basic behavior of the control signals. figure 4. sdram read access (cas latency = 3; burst length = 4) e_clk ta tw td tr ti ta tw td tr notcsi ale e_d add 1 read access write access add 2 dout ebi din notrdyrcv w/notr eaact earw eapre s_clk s_ncs s_nras s_ncas s_nwe s_dqm[1:0] s_a[11:0] s_q[15:0] .com .com .com .com .com 4 .com u datasheet
15/25 MTC20136 figure 5. sdram write access (cas latency = 3; burst length = 4) memory following features are provided for memory access (sram or feprom) : ? 16 bit databus and 20 bit address bus giving 1mbyte address space per chip select ? control signals : e_ncs[0:1], e_noe, e_nwe0, e_nwe1 ? setup and wait state insertion ? 8, 16 and 32 bit access by MTC20136 to 8 or 16 bit memory according to little endian convention figure 6. ebi memory access (32-bit word r/w to 16 bit memory), maximum speed timing eaact earw eapre s_clk s_ncs s_nras s_ncas s_nwe s_dqm[1:0] s_a[11:0] s_q[15:0] ebi e_ncsi e_noe e_nweo e_nwe1 e_a[19:2] a1[19:2] a2[19:2] e_a[1:0] 00 10 00 10 e_d[15:0] lsb msb msb lsb .com .com .com .com .com 4 .com u datasheet
MTC20136 16/25 ebi interface timing all timing parameters are specified at a load of 100 pf, all the electrical levels are cmos compatible. table 2. all signals table 3. ebi signal timing with respect to e_clk ctrle the ctrl-e interface is an adsl-oriented mailbox system to exchange control and status messages be- tween MTC20136 and an external controller. it consists of a mailbox and a physical interface. the mailbox has two 8-bit command registers to pass commands from the MTC20136 internal controller bus (asb) to ctrl-e (rxcommand) and from ctrl-e to asb (txcommand), and two status registers (rxcomav and tx- comav) to indicate the status of the command register. data associated with a command can be ex- changed using a common ctrledatabuffer. a hardware semaphore mechanism is provided to allow control of data consistency of the ctrledatabuffer. figure 7. ctrl-e interface controller principle symbol parameters min typ max unit t r ,t f rise and fall time (10% - 90%) 3 ns ci input load 10 pf co output load 100 pf symbol parameters min max unit t dh data input hold time from e_clk 3 ns t ds data input setup time to e_clk 10 ns t dd data/address output valid/tri-state delay from e_clk 10 ns t wrd ale delay from e_clk 6 ns t oed notoe delay from e_clk 6 ns t wed notwei delay from e_clk (falling edge) 6 ns t wrd w/notr delay from e_clk 3 10 ns t csd notcsi delay from e_clk 3 10 ns ctrl-e physical interface ctrl-e mailbox ctrledatabuffer (512*8 bit dual port ram) semaphore rxcomav txcomav rxcommand txcommand mailbox interrupt controller ctrl-e serial interface generic parallel interface tx rx d_selctrle i/o mrd mwr ma[8:0] md[7:0] mq[7:0] ctrlelnt1 ctrlelnt0 asb to it- controller .com .com .com .com .com 4 .com u datasheet
17/25 MTC20136 the ctrl-e physical interface between the mailbox and an external controller can be used in one of two modes: as a dedicated serial bus interface or as a generic parallel bus interface. selection between serial and parallel mode is done with an external mode strap, io pins are shared. ctrl-e mailbox the ctrl-e mailbox occupies a 512 byte memory map accessible by the ctrl-e physical interface and by the asb bus. the mailbox memory map is given in table 4. an external interrupt can be generated by the mailbox interrupt controller. a full description of the ctrle protocol and use of the ctrle mailbox is available in the ?ctrle inter- face specifications? documents, available separately. table 4. ctrl-e controller memory map: field acc mailbox address ma[8:0] size(bit) initial function txcommand rw 000 h 800 h command written by ctrl-e, read by asb rxcommand rw 001 h 800 h command written by asb, read by ctrl-e txcomav rw 002 h 10 b 1-bit register : 1 if tx command available rxcomav rw 003 h 10 b 1-bit register : 1 if rx command available semaphore pv 004 h 200 b semaphore for access to written by asb, read by ctrl-e ctrledatabuffer rw 005 h -1ff h 800 h 507x8 bit data buffer .com .com .com .com .com 4 .com u datasheet
MTC20136 18/25 ctrl-e semaphore a simple semaphore mechanism is provided to allow control of the data consistency of the ctrle- databuffer. one mailbox address is defined as a two-bit semaphore register protected by control logic to prevent unallowed write accesses to this register. before the databuffer is read or written by one of the two interfaces (asb or ctrl-e) this interface should perform a ?p-operation? on the semaphore. after a read or write of the databuffer the interface should do a ?v-operation? releasing the semaphore. p and v operations are performed by write and read accesses to the semaphore register. the semaphore will be updated as shown in table 5. each semaphore operation (p or v) consists of two consecutive actions that don?t have to be atomic : a)write the correct value to the semaphore address (see table 5) b)read the value in the semaphore address. if the value read is different from the value writen the p or v operation was not succesfull and should be tried again. table 5. semaphore p and v operations: new value after write by asb or ctrl-e the databuffers can be accessed without using the semaphore mechanism if data consistency is guaran- teed in another way. if other values are written to the semaphore address than the values listed the write will not be performed. ctrl-e physical interface two parallel bus modes are defined to support both motorola-compatible and intel-compatible timing and control signals. this interface specification is compliant to utopia level 2 parallel management interface. selection of the ctrl-e physical interface bus mode is done with the c_mode[1:0] input pins : table 6. bus mode selected with c_mode[1:0] inputs semaphore operation originator write value previous semaphore value semaphore free semaphore taken by asb ctrl-e 00 b 01 b 11 b pasb 01 b 01 b 01 b 11 b ctrl-e 11 b 11 b 01 b 11 b vasb 00 b 00 b 00 b 11 b ctrl-e 00 b 00 b 01 b 00 b c_mode[1] c_mode[0] description 0 0 motorola-type parallel interface 0 1 intel-type parallel interface 11reserved 10reserved .com .com .com .com .com 4 .com u datasheet
19/25 MTC20136 generic parallel interface the two parallel bus modes differ only in the definition of 3 control signals: busmode 0 provides a read/ write selector, a data strobe and a ready acknowledge. busmode 1 provides a read strobe, a write strobe and a ready acknowledge. the signal definition is shown in following table: table 7. ctrl-e interface signals in parallel interface modes write cycle timing figure 8. ctrl-e interface: write cycle timing in parallel modes 0 and 1 signal name type function pin c_a[8:0] i address bus c_a[8:0] c_d[7:0] io byte wide bidirectional data bus c_d[7:0] c_notcs i chip select c_notcs c_notint oz interrupt output, derived from ctrleint1 signal from mailbox : low when ctrleint1 is low, else tri-stated c_notint mode 0 : motorola-compatible mode c_mode[1:0] i 00 b c_mode[1:0] c_rd/notwr i read access if 1, write access if 0 c_notwr c_notds i data strobe c_notrd c_notdtack oz bus cycle ready indication, indicates that data on bus can be sampled or removed c_notrdy mode 1 : intel-compatible mode c_mode[1:0] i 01 b c_mode[1:0] c_notwr i write cycle indication c_notwr c_notrd i read cycle indication c_notrd c_notrdy oz bus cycle ready indication, indicates that data on bus can be sampled or removed, same as in mode 0 c_notrdy t1 c_a[8:0] c_d[7:0] c_notcs c_rd/notwr c_notds c_notdtack c_notwr mode 0 c_notrd c_notrdy t2 t7 t6 t3 t8 t4 t5 t9 mode 1 .com .com .com .com .com 4 .com u datasheet
MTC20136 20/25 table 8. write cycle timing in parallel modes 0 and 1 read cycle timing figure 9. ctrl-e interface: read cycle timing in parallel modes 0 and 1 table 9. read cycle timing in parallel modes 0 and 1 symbol description min max unit t1 c_a setup to c_notds (c_notwr) low 0 ns t2 c_notcs, c_rd/notwr setup to c_notds (c_notwr) low 0 ns t3 c_notds (c_notwr) pulse width 215 ns t4 c_d setup to c_notds (c_notwr) high 15 ns t5 c_a, c_d hold from c_notds (c_notwr) high 5 ns t6 c_notdtack (c_notrdy) valid from c_notds (c_notwr) low 15 ns t7 c_notdtack (c_notrdy) tri-state from c_notds (c_notwr) high 15 ns t8 c_notcs, c_rd/notwr hold from c_notds (c_notwr) high 0 ns t9 c_notcs high to c_notcs low 100 ns symbol description min max unit t1 c_a setup to c_notds (c_notrd) low 0 ns t2 c_notcs, c_rd/notwr setup to c_notds (c_notrd) low 0 ns t3 c_notds (c_notrd) pulse width 215 ns t4 c_d valid from c_notdtack (c_notrdy) low 10 ns t5 c_a, hold from c_notds (c_notrd) high 0 ns t6 c_notdtack (c_notrdy) valid from c_notds (c_notrd) high 15 ns t7 c_notdtack (c_notrdy) tri-state from c_notds (c_notrd) high 10 ns t8 c_notcs, c_rd/notwr hold from c_notds (c_notrd) high 10 ns t9 data tri-state from c_notds (c_notrd) high 90 100 ns t10 data tri-state from c_notcs high 5 15 ns t11 c_notcs high to c_notcs low (min. time between 2 accesses) 100 ns t1 c_a[8:0] c_d[7:0] c_notcs c_rd/notwr c_notds c_notdtack c_notrd mode 0 c_notwr c_notrdy t2 t7 t6 t3 t8 t4 t5 t11 t10 t9 mode 1 .com .com .com .com .com 4 .com u datasheet
21/25 MTC20136 peripherals uart two identical uarts are implemented in MTC20136. they offer similar functionality to the standard 16c550 device. they can support bit rates of up to 115.2 k bps and contain two 16 byte fifos for receive and transmit. general purpose i/os four pins are available for general purpose ios, two are used as inputs to specify the boot configuration and two are output under sw control. the latter can be used for instance to drive external leds. reset the MTC20136 has an asynchronous, active-low reset pin. an external clock is required to leave the reset state. clock the MTC20136 is operated from the 35.328mhz master clock, also used by the other dynamite chips. electrical specifications generic the values presented in the following table apply for all inputs and/or outputs unless specified otherwise. specifically they are not influenced by the choice between cmos or ttl levels. table 10. io buffers generic dc characteristics table 11. io buffers dynamic characteristics dc electrical characteristics all voltages are referenced to vss, unless otherwise specified, positive current is towards the device symbol parameter test conditions min typ max unit i in input leakage current v in = v ss , v dd , no pull up/pull down -1 1 a i oz tristate leakage current v in = v ss , v dd , no pull up/pull down -1 1 a i pu pull up current v in = v ss -25 -66 -125 a i pd pull down current v in = v dd 25 66 125 a r pu pull up resistance v in = v ss 50 kohm r pd pull down resistance v in = v dd 50 kohm dc electrical characteristics, important for transient but measured at (near) dc all voltages are referenced to vss, unless otherwise specified, positive current is towards the device symbol parameter test conditions min typ max unit c in input capacitance @f = 1mhz 5 pf di/dt current derivative 8 ma driver, slew rate control 8 ma driver, no slew rate control 23.5 ma/ns 89 ma/ns i peak peak current 8 ma driver, slew rate control 8 ma driver, no slew rate control 85 ma 100 ma c out output capacitance (also bidirectional and tristate drivers) @f = 1mhz 7 pf .com .com .com .com .com 4 .com u datasheet
MTC20136 22/25 input/output cmos generic characteristics the values presented in the following table apply for all cmos inputs and/ or outputs unless specified oth- erwise. table 12. cmos io buffers generic characteristics the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the avail- able values are 2, 4 and 8 ma. input/output ttl generic characteristics the values presented in the following table apply for all ttl inputs and/or outputs unless specified other- wise. table 13. ttl io buffers generic characteristics the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the avail- able values are currently 2, 4 and 8 ma. operating conditions table 14. operating conditions dc electrical characteristics all voltages are referenced to vss, unless otherwise specified, positive current is towards the device symbol parameter test conditions min typ max unit v il low level input voltage 0.2* v dd v v ih high level input voltage 0.8*v dd v v hy schmitt trigger hysteresis slow edge < 1 v/ms, only for schmitx 0.8 v v ol low level output voltage i out = xma[ 0.4 v v oh high level output voltage i out = -xma[ 0.85*v dd v dc electrical characteristics all voltages are referenced to vss, unless otherwise specified, positive current is towards the device symbol parameter test conditions min typ max unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v ilhy low level threshold, falling slow edge < 1 v/ms 0.9 1.35 v v ihhy high level threshold, rising slow edge < 1 v/ms 1.3 1.9 v v hy schmitt trigger hysteresis slow edge < 1 v/ms 0.4 0.7 v v ol low level output voltage i out = xma[ 0.4 v v oh high level output voltage i out = -xma[ 2.4 v maximum ratings symbol parameter test conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v t amb ambient temperature1m/s airflow -40 +85 c p power dissipation 300 400 mw .com .com .com .com .com 4 .com u datasheet
23/25 MTC20136 pqfp144 dim. mm inch min. typ. max. min. typ. max. a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.135 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 22.75 0.896 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 e3 22.75 0.896 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) a a2 a1 b c 36 37 72 73 108 109 144 e3 d3 e1 e d1 d e 1 k b pqfp144 l l1 seating plane 0.10mm .004 outline and mechanical data .com .com .com .com .com 4 .com u datasheet
MTC20136 24/25 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.210 1.700 0.047 0.067 a1 0.270 0.010 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.02 0.021 d 11.85 12.00 12.15 0.466 0.472 0.478 d1 10.40 0.409 e 11.85 12.00 12.15 0.466 0.472 0.478 e1 10.40 0.409 e 0.720 0.800 0.880 0.028 0.031 0.034 f 0.650 0.800 0.950 0.025 0.031 0.037 ddd 0.120 0.004 lfbga160 l ow profile f ine pitch b all g rid a rray 7254214 a body: 12 x 12 x 1.7mm .com .com .com .com .com 4 .com u datasheet
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